EMBEDDED FOLIO

ISSUE 001 · RISC ARCHITECTURE
EMBEDDED SYSTEMS WORLD

Visual concept guide · Based on the original LinkedIn infographic

Illustrated summary: regular decoding, load-store register model, simpler hardware and pipelining

Updated from the original infographic for accuracy: Cortex-M Thumb instructions can be 16 or 32 bits long; instruction timing varies.

ISSUE 001 · FRONTembeddedsysworld.com

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ISSUE 001 · HOW IT WORKS
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See it in action · Cortex-M example

Load. Compute. Store.

A typical register-based sequence separates the memory access from the arithmetic operation.

One increment operation

ldr  r0, [r1]     ; Read from memory
adds r0, r0, #1   ; Add 1 in a register
str  r0, [r1]     ; Write back to memory

r1 holds an address. r0 temporarily holds the value. The CPU does not have to run an arithmetic instruction directly on the memory location.

Memory→Registers
+ ALU→Memory

How execution moves through a simple pipeline

Stage	Purpose
Fetch	Obtain instruction bytes from memory.
Decode	Interpret the operation and operands.
Execute	Perform an ALU operation or memory access.

This is a conceptual three-stage view. Different microcontrollers have different pipelines, stalls and instruction timings.

Key takeaway
RISC is useful in microcontrollers because its regular, register-oriented approach enables efficient core designs. It is not a guarantee of fixed instruction width, one-cycle execution or deterministic timing by itself.

Quick check

Question: In the example, why is adds r0, r0, #1 performed after ldr?

Answer: The ALU adds using register operands; the load instruction first brings the memory value into r0.

ISSUE 001 · BACKOne concept. Two sides. Five minutes.